1. Field of the Invention
The present invention generally relates to signals processing technology in the application of display systems. More particular, the present invention relates to an apparatus and method of clock recovery for sampling analog signals provided to an analog-to-digital converter (ADC).
2. Description of Related Art
Digital image processing is the most popular method used in display system. However, the drawback of digital signal processing is the use of high bit counts while digital signals are transmitted between different systems. In addition, a great deal of bandwidth and processing power are required for data transfer therebetween. Therefore, the use of analog signals is the prime solution in the application of data transmission between different system interfaces. For example, eight data lines are required for the transmission of a 8-bit digital pixel signal of 256 colors, while one data line provided for the transmission of analog signal is sufficient. Accordingly, the digital-to-analog converter (DAC) and the analog-to-digital converter (ADC) have become the most important components for connecting two digital systems. For example, digital pixel data are generated by a graphics chip and converted by the DAC into the associated analog pixel signals in a computer. The analog pixel signals are transmitted, through a cable, to the ADC of a back-end digital display device. The ADC receives the analog pixel signals and converts them into the associated digital pixel signals for image display. In other words, the ADC is used to generate the digital pixel signals corresponding to the digital pixel data.
The analog pixel signals coming from a graphics system, such as a personal computer (PC), are generated in synchronization with an internal clock thereof. Therefore, it is required to provide a sample clock with substantially the same frequency as that of the internal clock for analog signal processing at the back-end display device. The quality of the image to be displayed on the back-end display is heavily relied upon whether the analog pixel signals are in synchronization with the sample clock.
However, in the personal computer, no such sample clock will be so provided that the sample clock should be recovered from a reference signal, such as a horizontal synchronization signal, hereinafter Hsync. The Hsync signal is provided with a time period which is Htt times the pixel clock period, wherein Htt designates the horizontal total pixel counts for each line. Accordingly, the recovered clock should have a frequency of (Hsync frequency)×(Htt). However, Htt usually varies with different display modes or even different graphic chips while performing at the same display mode. Therefore, mode detection is needed to assist the display device to estimate the value of Htt. Conventionally, the mode detection uses a clock with a fixed frequency to count the Hsync signal and to generate a count value. The count value can be employed to look up the VESA (Video Electronic Standards Association) standard table so as to obtain the possible display mode (XGA, SVGA, etc.). But the conventional method cannot calculate the exact Htt because the clock with the fixed frequency is unrelated to the sample clock used by the back-end display device.
In addition, phase detection algorithm can be used for sample clock recovery devicey by means of generating an estimated value of Htt and then using the estimated value to approach the exact one. A sum of Σ|pixel(n)−pixel(n+1)| is a simple way to implement the phase detection algorithm. However, the pixel difference method is useful for most kinds of patterns, but unfavorable for special patterns like block pattern, linear piece pattern, or the like. Moreover, the use of Σ|pixel(n)−pixel(n+1)| cannot identify incorrect maxima and slope change.